ASIC Physical Designers

Requirement Title: ASIC Physical Designers


No of position: 1

Experience: 5.00 - 12.00 (years)

Availability: Short Period

Location: Singapore

Status: Open

Job Description

ASIC Physical Designers - Contract

RESPONSIBILITIES CW will assist the DE Leads in executing DFT (Design for Test) tasks including scan insertion, ATPG, Scan simulations and MBIST simulations. Primary Skills

Verilog RTL skills, DFT Compiler experience, Mentor Graphics Tessent tool experience, Cadence NCSIM, scripting in PERL and Shell. Unix. Communication and team skills. Critical help needed for DFT tasks in S8 and IBIS

Secondary Skills

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