Requirement Title: ASIC Physical Designers
Function:
No of position: 1
Experience: 5.00 - 12.00 (years)
Availability: Short Period
Location: Singapore
Status: Open
Verilog RTL skills, DFT Compiler experience, Mentor Graphics Tessent tool experience, Cadence NCSIM, scripting in PERL and Shell. Unix. Communication and team skills. Critical help needed for DFT tasks in S8 and IBIS
Secondary Skills